/** * @file tpl_memory_protection.c * * @section descr File description * * Trampoline processor dependant memory protection for STM32F4VG407 CORTEX-M4 mpu. * * @section copyright Copyright * * Trampoline OS * * Trampoline is copyright (c) IRCCyN 2005-2009 * Autosar extension is copyright (c) IRCCyN and ESEO 2007-2009 * Trampoline and its Autosar extension are protected by the * French intellectual property law. * * This software is distributed under a dual licencing scheme * 1 - The Lesser GNU Public Licence v2 (LGPLv2) * 2 - The BSD Licence * * @section infos File informations * * $Date$ * $Rev$ * $Author$ * $URL$ */ #ifndef TPL_MEMORY_PROTECTION_H #define TPL_MEMORY_PROTECTION_H #include "tpl_os_internal_types.h" #include "tpl_os_definitions.h" #include "tpl_os_mem_prot.h" #include "stm32f4xx.h" #define MPU_DEFS_RASR_SIZE_32B (0x04 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_64B (0x05 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_128B (0x06 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_256B (0x07 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_512B (0x08 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_1KB (0x09 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_2KB (0x0A << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_4KB (0x0B << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_8KB (0x0C << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_16KB (0x0D << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_32KB (0x0E << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_64KB (0x0F << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_128KB (0x10 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_256KB (0x11 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_512KB (0x12 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_1MB (0x13 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_2MB (0x14 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_4MB (0x15 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_8MB (0x16 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_16MB (0x17 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_32MB (0x18 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_64MB (0x19 << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_128MB (0x1A << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_256MB (0x1B << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_512MB (0x1C << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_1GB (0x1D << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_2GB (0x1E << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASR_SIZE_4GB (0x1F << MPU_RASR_SIZE_Pos) #define MPU_DEFS_RASE_AP_NO_ACCESS (0x0 << MPU_RASR_AP_Pos) #define MPU_DEFS_RASE_AP_PRIV_RW (0x1 << MPU_RASR_AP_Pos) #define MPU_DEFS_RASE_AP_PRIV_RW_USER_RO (0x2 << MPU_RASR_AP_Pos) #define MPU_DEFS_RASE_AP_FULL_ACCESS (0x3 << MPU_RASR_AP_Pos) #define MPU_DEFS_RASE_AP_PRIV_RO (0x5 << MPU_RASR_AP_Pos) #define MPU_DEFS_RASE_AP_RO (0x6 << MPU_RASR_AP_Pos) #define MPU_DEFS_NORMAL_MEMORY_WT (MPU_RASR_C_Msk) #define MPU_DEFS_NORMAL_MEMORY_WB (MPU_RASR_C_Msk | MPU_RASR_B_Msk) #define MPU_DEFS_NORMAL_SHARED_MEMORY_WT (MPU_RASR_C_Msk | MPU_RASR_S_Msk) #define MPU_DEFS_NORMAL_SHARED_MEMORY_WB (MPU_DEFS_NORMAL_MEMORY_WB | MPU_RASR_S_Msk) #define MPU_DEFS_SHARED_DEVICE (MPU_RASR_B_Msk) #define MPU_DEFS_STRONGLY_ORDERED_DEVICE (0x0) #define MPU_DEFS_NB_REGION_USED (2) extern CONSTP2CONST(tpl_mem_prot_desc, AUTOMATIC, OS_CONST) tpl_mp_table[TASK_COUNT+ISR_COUNT+1]; /** * This function prepares MMU data ѕtructures in memory * to reflect memory protection scheme generated by goil * * @note this does not starts the MMU */ extern FUNC(void, OS_CODE) tpl_init_mp(); /** * sets memory protection to privileged mode (no memory protection) */ extern FUNC(void, OS_CODE) tpl_kernel_mp (void); /** * turn back to memory protection configuration according to the running * process. If it is (or becomes) trusted, MMU is kept disabled (it should * already have been disabled at kernel enter */ extern FUNC(void, OS_CODE) tpl_user_mp (void); /** * Set the memory protection for a process */ extern FUNC(void, OS_CODE) tpl_set_process_mp (tpl_task_id this_process); #endif /* TPL_MEMORY_PROTECTION_H */