Index of /rcar/s4sk/build/build-s4sk-gateway/tmp/work-shared/gcc-9.3.0-r0/gcc-9.3.0/gcc/testsuite/gcc.target/arm/simd

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[TXT]fp16fml_high.c2020-03-12 20:07 1.0K 
[TXT]fp16fml_lane_high.c2020-03-12 20:07 2.0K 
[TXT]fp16fml_lane_low.c2020-03-12 20:07 2.0K 
[TXT]fp16fml_low.c2020-03-12 20:07 1.0K 
[TXT]neon-vrndx_f32_1.c2020-03-12 20:07 392  
[TXT]neon-vrndxq_f32_1.c2020-03-12 20:07 395  
[TXT]simd.exp2020-03-12 20:07 1.4K 
[TXT]vdot-compile.c2020-03-12 20:07 1.4K 
[TXT]vdot-exec.c2020-03-12 20:07 1.8K 
[TXT]vect-dot-qi.h2020-03-12 20:07 332  
[TXT]vect-dot-s8.c2020-03-12 20:07 322  
[TXT]vect-dot-u8.c2020-03-12 20:07 324  
[TXT]vextQf32_1.c2020-03-12 20:07 355  
[TXT]vextQp8_1.c2020-03-12 20:07 353  
[TXT]vextQp16_1.c2020-03-12 20:07 355  
[TXT]vextQp64_1.c2020-03-12 20:07 726  
[TXT]vextQs8_1.c2020-03-12 20:07 353  
[TXT]vextQs16_1.c2020-03-12 20:07 355  
[TXT]vextQs32_1.c2020-03-12 20:07 355  
[TXT]vextQs64_1.c2020-03-12 20:07 355  
[TXT]vextQu8_1.c2020-03-12 20:07 353  
[TXT]vextQu16_1.c2020-03-12 20:07 355  
[TXT]vextQu32_1.c2020-03-12 20:07 355  
[TXT]vextQu64_1.c2020-03-12 20:07 355  
[TXT]vextf32_1.c2020-03-12 20:07 353  
[TXT]vextp8_1.c2020-03-12 20:07 350  
[TXT]vextp16_1.c2020-03-12 20:07 353  
[TXT]vextp64_1.c2020-03-12 20:07 505  
[TXT]vexts8_1.c2020-03-12 20:07 350  
[TXT]vexts16_1.c2020-03-12 20:07 353  
[TXT]vexts32_1.c2020-03-12 20:07 353  
[TXT]vexts64_1.c2020-03-12 20:07 512  
[TXT]vextu8_1.c2020-03-12 20:07 350  
[TXT]vextu16_1.c2020-03-12 20:07 353  
[TXT]vextu32_1.c2020-03-12 20:07 353  
[TXT]vextu64_1.c2020-03-12 20:07 517  
[TXT]vmaxnm_f32_1.c2020-03-12 20:07 4.0K 
[TXT]vmaxnmq_f32_1.c2020-03-12 20:07 4.1K 
[TXT]vminnm_f32_1.c2020-03-12 20:07 4.0K 
[TXT]vminnmq_f32_1.c2020-03-12 20:07 4.1K 
[TXT]vrev16p8_1.c2020-03-12 20:07 315  
[TXT]vrev16qp8_1.c2020-03-12 20:07 318  
[TXT]vrev16qs8_1.c2020-03-12 20:07 318  
[TXT]vrev16qu8_1.c2020-03-12 20:07 318  
[TXT]vrev16s8_1.c2020-03-12 20:07 315  
[TXT]vrev16u8_1.c2020-03-12 20:07 315  
[TXT]vrev32p8_1.c2020-03-12 20:07 315  
[TXT]vrev32p16_1.c2020-03-12 20:07 318  
[TXT]vrev32qp8_1.c2020-03-12 20:07 318  
[TXT]vrev32qp16_1.c2020-03-12 20:07 321  
[TXT]vrev32qs8_1.c2020-03-12 20:07 318  
[TXT]vrev32qs16_1.c2020-03-12 20:07 321  
[TXT]vrev32qu8_1.c2020-03-12 20:07 318  
[TXT]vrev32qu16_1.c2020-03-12 20:07 321  
[TXT]vrev32s8_1.c2020-03-12 20:07 315  
[TXT]vrev32s16_1.c2020-03-12 20:07 318  
[TXT]vrev32u8_1.c2020-03-12 20:07 315  
[TXT]vrev32u16_1.c2020-03-12 20:07 318  
[TXT]vrev64f32_1.c2020-03-12 20:07 318  
[TXT]vrev64p8_1.c2020-03-12 20:07 315  
[TXT]vrev64p16_1.c2020-03-12 20:07 318  
[TXT]vrev64qf32_1.c2020-03-12 20:07 321  
[TXT]vrev64qp8_1.c2020-03-12 20:07 318  
[TXT]vrev64qp16_1.c2020-03-12 20:07 321  
[TXT]vrev64qs8_1.c2020-03-12 20:07 318  
[TXT]vrev64qs16_1.c2020-03-12 20:07 321  
[TXT]vrev64qs32_1.c2020-03-12 20:07 321  
[TXT]vrev64qu8_1.c2020-03-12 20:07 318  
[TXT]vrev64qu16_1.c2020-03-12 20:07 321  
[TXT]vrev64qu32_1.c2020-03-12 20:07 321  
[TXT]vrev64s8_1.c2020-03-12 20:07 315  
[TXT]vrev64s16_1.c2020-03-12 20:07 318  
[TXT]vrev64s32_1.c2020-03-12 20:07 318  
[TXT]vrev64u8_1.c2020-03-12 20:07 315  
[TXT]vrev64u16_1.c2020-03-12 20:07 318  
[TXT]vrev64u32_1.c2020-03-12 20:07 318  
[TXT]vtrnf32_1.c2020-03-12 20:07 327  
[TXT]vtrnp8_1.c2020-03-12 20:07 324  
[TXT]vtrnp16_1.c2020-03-12 20:07 327  
[TXT]vtrnqf32_1.c2020-03-12 20:07 329  
[TXT]vtrnqp8_1.c2020-03-12 20:07 326  
[TXT]vtrnqp16_1.c2020-03-12 20:07 329  
[TXT]vtrnqs8_1.c2020-03-12 20:07 326  
[TXT]vtrnqs16_1.c2020-03-12 20:07 329  
[TXT]vtrnqs32_1.c2020-03-12 20:07 329  
[TXT]vtrnqu8_1.c2020-03-12 20:07 326  
[TXT]vtrnqu16_1.c2020-03-12 20:07 329  
[TXT]vtrnqu32_1.c2020-03-12 20:07 329  
[TXT]vtrns8_1.c2020-03-12 20:07 324  
[TXT]vtrns16_1.c2020-03-12 20:07 327  
[TXT]vtrns32_1.c2020-03-12 20:07 327  
[TXT]vtrnu8_1.c2020-03-12 20:07 324  
[TXT]vtrnu16_1.c2020-03-12 20:07 327  
[TXT]vtrnu32_1.c2020-03-12 20:07 327  
[TXT]vuzpf32_1.c2020-03-12 20:07 327  
[TXT]vuzpp8_1.c2020-03-12 20:07 324  
[TXT]vuzpp16_1.c2020-03-12 20:07 327  
[TXT]vuzpqf32_1.c2020-03-12 20:07 329  
[TXT]vuzpqp8_1.c2020-03-12 20:07 326  
[TXT]vuzpqp16_1.c2020-03-12 20:07 329  
[TXT]vuzpqs8_1.c2020-03-12 20:07 326  
[TXT]vuzpqs16_1.c2020-03-12 20:07 329  
[TXT]vuzpqs32_1.c2020-03-12 20:07 329  
[TXT]vuzpqu8_1.c2020-03-12 20:07 326  
[TXT]vuzpqu16_1.c2020-03-12 20:07 329  
[TXT]vuzpqu32_1.c2020-03-12 20:07 329  
[TXT]vuzps8_1.c2020-03-12 20:07 324  
[TXT]vuzps16_1.c2020-03-12 20:07 327  
[TXT]vuzps32_1.c2020-03-12 20:07 327  
[TXT]vuzpu8_1.c2020-03-12 20:07 324  
[TXT]vuzpu16_1.c2020-03-12 20:07 327  
[TXT]vuzpu32_1.c2020-03-12 20:07 327  
[TXT]vzipf32_1.c2020-03-12 20:07 327  
[TXT]vzipp8_1.c2020-03-12 20:07 324  
[TXT]vzipp16_1.c2020-03-12 20:07 327  
[TXT]vzipqf32_1.c2020-03-12 20:07 329  
[TXT]vzipqp8_1.c2020-03-12 20:07 326  
[TXT]vzipqp16_1.c2020-03-12 20:07 329  
[TXT]vzipqs8_1.c2020-03-12 20:07 326  
[TXT]vzipqs16_1.c2020-03-12 20:07 329  
[TXT]vzipqs32_1.c2020-03-12 20:07 329  
[TXT]vzipqu8_1.c2020-03-12 20:07 326  
[TXT]vzipqu16_1.c2020-03-12 20:07 329  
[TXT]vzipqu32_1.c2020-03-12 20:07 329  
[TXT]vzips8_1.c2020-03-12 20:07 324  
[TXT]vzips16_1.c2020-03-12 20:07 327  
[TXT]vzips32_1.c2020-03-12 20:07 327  
[TXT]vzipu8_1.c2020-03-12 20:07 324  
[TXT]vzipu16_1.c2020-03-12 20:07 327  
[TXT]vzipu32_1.c2020-03-12 20:07 327