/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2021 Renesas Electronics Corp.
 */
#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* r8a779g0 CPG Core Clocks */
#define R8A779G0_CLK_Z2			0
#define R8A779G0_CLK_ZR0		1
#define R8A779G0_CLK_ZR1		2
#define R8A779G0_CLK_ZR2		3
#define R8A779G0_CLK_ZX			4
#define R8A779G0_CLK_ZT			5
#define R8A779G0_CLK_ZTR		6
#define R8A779G0_CLK_ZS			7
#define R8A779G0_CLK_CL			8
#define R8A779G0_CLK_S0D1_VIO		9
#define R8A779G0_CLK_S0D2_VIO		10
#define R8A779G0_CLK_S0D4_VIO		11
#define R8A779G0_CLK_S0D8_VIO		12
#define R8A779G0_CLK_S0D1_VC		13
#define R8A779G0_CLK_S0D2_VC		14
#define R8A779G0_CLK_S0D4_VC		15
#define R8A779G0_CLK_S0D1_HSC		16
#define R8A779G0_CLK_S0D2_HSC		17
#define R8A779G0_CLK_S0D4_HSC		18
#define R8A779G0_CLK_S0D8_HSC		19
#define R8A779G0_CLK_SVD1_VIP		20
#define R8A779G0_CLK_SVD2_VIP		21
#define R8A779G0_CLK_SVD1_IR		22
#define R8A779G0_CLK_SVD2_IR		23
#define R8A779G0_CLK_S0D2		24
#define R8A779G0_CLK_S0D3		25
#define R8A779G0_CLK_S0D4		26
#define R8A779G0_CLK_S0D2_RT		27
#define R8A779G0_CLK_S0D3_RT		28
#define R8A779G0_CLK_S0D4_RT		29
#define R8A779G0_CLK_S0D6_RT		30
#define R8A779G0_CLK_S0D24_RT		31
#define R8A779G0_CLK_S0D2_PER		32
#define R8A779G0_CLK_S0D3_PER		33
#define R8A779G0_CLK_S0D4_PER		34
#define R8A779G0_CLK_S0D6_PER		35
#define R8A779G0_CLK_S0D12_PER		36
#define R8A779G0_CLK_S0D24_PER		37
#define R8A779G0_CLK_S0D2_MM		38
#define R8A779G0_CLK_S0D4_MM		39
#define R8A779G0_CLK_S0D2_CC		40
#define R8A779G0_CLK_S0D2_U3DG		41
#define R8A779G0_CLK_S0D4_U3DG		42
#define R8A779G0_CLK_CL16M_HSC		43
#define R8A779G0_CLK_CL16M		44
#define R8A779G0_CLK_CL16M_RT		45
#define R8A779G0_CLK_CL16M_PER		46
#define R8A779G0_CLK_CL16M_MM		47
#define R8A779G0_CLK_SD0H		48
#define R8A779G0_CLK_SD0		49
#define R8A779G0_CLK_RPC		50
#define R8A779G0_CLK_RPCD2		51
#define R8A779G0_CLK_MSO		52
#define R8A779G0_CLK_CANFD		53
#define R8A779G0_CLK_CSI		54
#define R8A779G0_CLK_FRAY		55
#define R8A779G0_CLK_IPC		56
#define R8A779G0_CLK_POST		57
#define R8A779G0_CLK_POST2		58
#define R8A779G0_CLK_POST3		59
#define R8A779G0_CLK_POST4		60
#define R8A779G0_CLK_SASYNCPER		61
#define R8A779G0_CLK_SASYNCPERD1	62
#define R8A779G0_CLK_SASYNCPERD2	63
#define R8A779G0_CLK_SASYNCPERD4	64
#define R8A779G0_CLK_SASYNCRT		65
#define R8A779G0_CLK_IMPA		66
#define R8A779G0_CLK_IMPAD4		67
#define R8A779G0_CLK_VIOBUS		68
#define R8A779G0_CLK_VIOBUSD2	69
#define R8A779G0_CLK_VCBUS		70
#define R8A779G0_CLK_VCBUSD2	71
#define R8A779G0_CLK_DSIEXT		72
#define R8A779G0_CLK_DSIREF		73
#define R8A779G0_CLK_ADGH		74
#define R8A779G0_CLK_OSCCLK		75
#define R8A779G0_CLK_ZB3		76
#define R8A779G0_CLK_ZB3D2		77
#define R8A779G0_CLK_ZB3D4		78
#define R8A779G0_CLK_ZG			79
#define R8A779G0_CLK_CPEX		80
#define R8A779G0_CLK_CP			81
#define R8A779G0_CLK_CBFUSA		82
#define R8A779G0_CLK_Z0		83
#define R8A779G0_CLK_RCLK		84

#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */